DFT Engineer Quiz

1. Alright, let’s kick off — what’s the main goal of DFT in VLSI?

A) Speed up the design process B) Reduce area C) Improve chip aesthetics D) Improve testability of the design

2. What’s the most common testing method used in DFT?

A) Water flow test B) Scan-based testing C) X-ray testing D) Manual probing

3. Which DFT technique helps in shifting values in and out of flip-flops?

A) Memory test B) Scan chain C) BIST D) ATPG

4. What does ATPG stand for? You’ll hear this daily in DFT.

A) Automatic Test Pattern Generator B) All Transistor Power Grid C) Automatic Timing Power Generator D) Analog Test Power Gain

5. What is stuck-at fault modeling?

A) Testing only power B) Assuming a net is stuck at 0 or 1 C) Counting the number of flip-flops D) Compressing test data

6. Which of these is considered a major DFT challenge in complex designs?

A) Low power during scan B) Lack of colors in layout C) Too many memos D) Heavy metal layers

7. What does MBIST primarily test?

A) Flip-Flops B) Memories C) Power Grid D) Analog signals

8. Boundary Scan is mostly used for testing what?

A) Internal CPU B) External I/Os and PCB connectivity C) Embedded software D) Analog performance

9. What’s the purpose of a Test Compression Technique?

A) Change chip size B) Reduce test data volume C) Double the scan chains D) Increase power usage

10. Which of these is a standard used for boundary scan?

A) IEEE 1800 B) IEEE 1149.1 C) IEEE 802.3 D) IEEE 1687

11. What’s the major output generated by ATPG tools?

A) Verilog Code B) Test Patterns C) GDSII file D) Spice file

12. Which DFT technique can automatically run self-tests in silicon?

A) BIST B) PLL C) Clock Gating D) Placement

13. Which signal is essential to control the scan mode?

A) Clock Enable B) Scan Enable C) Reset D) Write Enable

14. Why do we insert scan chains in design?

A) Improve power B) Facilitate debugging and testing C) Optimize timing D) Reduce leakage

15. What’s the main concern with scan-based testing in terms of power?

A) Leakage B) IR drop due to high switching activity C) Heat sink size D) Frequency reduction

16. In Memory BIST, what’s a March Test used for?

A) Test flip-flops B) Detect memory faults C) Measure area D) Reduce power

17. Which tool is commonly used for DFT and ATPG?

A) Synopsys TetraMAX B) Photoshop C) AutoCAD D) MATLAB

18. What is the main function of JTAG?

A) Generate RTL B) Test PCB connections and enable debugging C) Power optimization D) Heat dissipation

19. What is the impact of adding too many scan chains?

A) Better power usage B) Increase area and congestion C) Reduce test coverage D) Improve analog performance

20. What’s IR Drop, which is often discussed during scan testing?

A) Increase in resistance B) Voltage drop due to high current draw C) Area reduction D) Silicon temperature increase

21. Which compression ratio is considered good in test compression?

A) 2x B) 5x C) 10x or more D) 1x

22. Which of these is an effect of not handling X-States properly in DFT?

A) Better speed B) Power reduction C) ATPG test failures D) More scan chains

23. What’s a Wrapper Cell in DFT?

A) Special cell for analog B) Wrapper around memory C) Cell added to enable boundary scan D) Cell that controls PLL

24. Which fault model targets delay-related issues?

A) Stuck-at B) Transition Fault C) Bridging Fault D) Power Fault

25. Finally, what is the main goal of IJTAG (IEEE 1687)?

A) Analog testing B) On-chip debug access to internal instruments C) Memory design D) DSP optimization

DFT Engineer Quiz

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